Thermal management of on-chip caches through power density minimization

Ja Chun Ku*, Serkan Ozdemir, Gokhan Memik, Yehea Ismail

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Scopus citations

Abstract

Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. However, these techniques mostly ignore the effects of temperature on the power consumption. In this paper, first we show that these power reduction techniques can be suboptimal when thermal effects are considered. Particularly, we propose a thermal-aware cache powerdown technique that minimizes the power density of the active parts by turning off alternating rows of memory cells instead of entire banks. The decrease in the power density lowers the temperature, which in return, reduces the leakage of the active parts. Simulations based on SPEC2000 benchmarks in a 70nm technology show that the proposed thermal-aware architecture can reduce the total energy consumption by 53% compared to a conventional cache, and 14% compared to a cache architecture with thermal-unaware power reduction scheme. Second, we show a block permutation scheme that can be used during the design of caches to maximize the distance between blocks with consecutive addresses. By maximizing the distance between consecutively accessed blocks, we minimize the power density of the hot spots in the cache, and hence reduce the peak temperature. This, in return, results in an average leakage power reduction of 8.7% compared to a conventional cache without affecting the dynamic power and the latency. Overall, both of our architectures add no extra run-time penalty compared to the thermalunaware power reduction schemes, yet they reduce the total energy consumption of a conventional cache by 53% and 5.6% on average, respectively.

Original languageEnglish (US)
Title of host publicationMICRO-38
Subtitle of host publicationProceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture
Pages283-293
Number of pages11
DOIs
StatePublished - 2005
EventMICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture - Barcelona, Spain
Duration: Nov 12 2005Nov 16 2005

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

OtherMICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture
CountrySpain
CityBarcelona
Period11/12/0511/16/05

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Thermal management of on-chip caches through power density minimization'. Together they form a unique fingerprint.

Cite this