Three-Dimensional Silicon Electronic Systems Fabricated by Compressive Buckling Process

Bong Hoon Kim, Jungyup Lee, Sang Min Won, Zhaoqian Xie, Jan Kai Chang, Yongjoon Yu, Youn Kyoung Cho, Hokyung Jang, Ji Yoon Jeong, Yechan Lee, Arin Ryu, Do Hoon Kim, Kun Hyuck Lee, Jong Yoon Lee, Fei Liu, Xueju Wang, Qingze Huo, Seunghwan Min, Di Wu, Bowen JiAnthony Banks, Jeonghyun Kim, Nuri Oh, Hyeong Min Jin, Seungyong Han, Daeshik Kang, Chi Hwan Lee, Young Min Song, Yihui Zhang, Yonggang Huang, Kyung In Jang*, John A. Rogers

*Corresponding author for this work

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

Recently developed approaches in deterministic assembly allow for controlled, geometric transformation of two-dimensional structures into complex, engineered three-dimensional layouts. Attractive features include applicability to wide ranging layout designs and dimensions along with the capacity to integrate planar thin film materials and device layouts. The work reported here establishes further capabilities for directly embedding high-performance electronic devices into the resultant 3D constructs based on silicon nanomembranes (Si NMs) as the active materials in custom devices or microscale components released from commercial wafer sources. Systematic experimental studies and theoretical analysis illustrate the key ideas through varied 3D architectures, from interconnected bridges and coils to extended chiral structures, each of which embed n-channel Si NM MOSFETs (nMOS), Si NM diodes, and p-channel silicon MOSFETs (pMOS). Examples in stretchable/deformable systems highlight additional features of these platforms. These strategies are immediately applicable to other wide-ranging classes of materials and device technologies that can be rendered in two-dimensional layouts, from systems for energy storage, to photovoltaics, optoelectronics, and others.

Original languageEnglish (US)
Pages (from-to)4164-4171
Number of pages8
JournalACS nano
Volume12
Issue number5
DOIs
StatePublished - May 22 2018

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Keywords

  • mechanical buckling
  • silicon diode
  • silicon transistor
  • three-dimensional electronics

ASJC Scopus subject areas

  • Materials Science(all)
  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

Kim, B. H., Lee, J., Won, S. M., Xie, Z., Chang, J. K., Yu, Y., Cho, Y. K., Jang, H., Jeong, J. Y., Lee, Y., Ryu, A., Kim, D. H., Lee, K. H., Lee, J. Y., Liu, F., Wang, X., Huo, Q., Min, S., Wu, D., ... Rogers, J. A. (2018). Three-Dimensional Silicon Electronic Systems Fabricated by Compressive Buckling Process. ACS nano, 12(5), 4164-4171. https://doi.org/10.1021/acsnano.8b00180