Timing verification with crosstalk for transparently latched circuits

Hai Zhou*

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review


Delay variation due to crosstalk has made timing analysis a hard problem. In sequential circuits with transparent latches, crosstalk makes the timing verification (also known as clock schedule verification) even harder. In this paper, we point out a false negative problem in current timing verification techniques and propose a new approach based on switching windows. In this approach, coupling delay calculations are combined naturally with latch timing iterations. A novel algorithm is given for timing verification with crosstalk in transparently latched circuits and primitive experiments show promising results.

Original languageEnglish (US)
Article number1253587
Pages (from-to)56-61
Number of pages6
JournalProceedings -Design, Automation and Test in Europe, DATE
StatePublished - Dec 1 2003
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Germany
Duration: Mar 3 2003Mar 7 2003

ASJC Scopus subject areas

  • Engineering(all)


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