Delay variation due to crosstalk has made timing analysis a hard problem. In sequential circuits with transparent latches, crosstalk makes the timing verification (also known as clock schedule verification) even harder. In this paper, we point out a false negative problem in current timing verification techniques and propose a new approach based on switching windows. In this approach, coupling delay calculations are combined naturally with latch timing iterations. A novel algorithm is given for timing verification with crosstalk in transparently latched circuits and primitive experiments show promising results.
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|State||Published - Dec 1 2003|
|Event||Design, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Germany|
Duration: Mar 3 2003 → Mar 7 2003
ASJC Scopus subject areas