Timing yield estimation using statistical static timing analysis

Min Pan*, Chris Chong Nuen Chu, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

16 Scopus citations


As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for high-performance circuit designs could reduce the excessive conservatism that is built into current timing design method. In this paper, we address the timing yield problem for sequential circuits and propose a statistical approach to handle it. In our approach, we consider the spatial and path reconvergence correlations between path delays, set-up time and hold time constraints, as well as clock skew due to process variations. We propose a method to get the timing yield based on the delay distributions of register-to-register paths in the circuit. On average, the timing yield results obtained by our approach have average errors of less than 1.0% in comparison with Monte Carlo simulation. Experimental results show that shortest path variations and clock skew due to process variations have considerable impact on circuit timing, which could bias the timing yield results. In addition, the correlation between longest and shortest path delays is not significant.

Original languageEnglish (US)
Article number1465124
Pages (from-to)2461-2464
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Dec 1 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: May 23 2005May 26 2005

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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