TY - GEN
T1 - Totem
T2 - 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001
AU - Compton, K.
AU - Hauck, S.
N1 - Funding Information:
This research was supported in part by Motorola, Inc., and DARPA. Katherine Compton was supported by an NSF Fellowship. Scott Hauck was supported by an NSF CAREER award. Thanks to the RaPiD team at the CS department of the University of Washington, especially Chris Fisher and Mike Scott, for fielding questions on the architecture and the compiler. Thanks also to University of Washington EE graduate students Akshay Sharma for the measure of RaPiD cells required to implement each netlist, and Shawn Phillips for help with RaPiD layout structures.
Funding Information:
This research was supported in part by Motorola, Inc., and DARPA. Katherine Compton was supported by an NSF Fellowship. Scott Hauck was supported by an NSF CAREER award.
Publisher Copyright:
© 2001 Non IEEE.
PY - 2001
Y1 - 2001
N2 - Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case, and miss optimization opportunities present if characteristics of the desired application set are known. We can therefore increase efficiency by restricting the structure to support a class or a specific set of algorithms, while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA. However, the manual creation of these customized reprogrammable architectures would be a labor-intensive process, leading to high design costs. Instead, we propose automatic reconfigurable architecture generation specialized to given application sets. The Totem custom reconfigurable array generator is our initial step in this direction.
AB - Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case, and miss optimization opportunities present if characteristics of the desired application set are known. We can therefore increase efficiency by restricting the structure to support a class or a specific set of algorithms, while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA. However, the manual creation of these customized reprogrammable architectures would be a labor-intensive process, leading to high design costs. Instead, we propose automatic reconfigurable architecture generation specialized to given application sets. The Totem custom reconfigurable array generator is our initial step in this direction.
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M3 - Conference contribution
AN - SCOPUS:84963954581
T3 - Proceedings - 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001
SP - 111
EP - 119
BT - Proceedings - 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 29 March 2001 through 2 April 2001
ER -