TY - GEN
T1 - Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
AU - Lin, Chuan
AU - Zhou, Hai
PY - 2005
Y1 - 2005
N2 - Latches are extensively used in high-performance sequential circuit designs to achieve high frequencies because of their good performance and time borrowing feature. However, the amount of timing uncertainty due to crosstalk accumulated through latches could be larger than the benefit gained by time borrowing. In this paper, we show that the trade-off between a latch and a flop can be leveraged in a sequential circuit design with crosstalk, so that the clock period is minimized by selecting a configuration of mixed latches and flops. A circular time representation is proposed to make coupling detection easier and more efficient. Experiments on our heuristic algorithm for finding an optimal configuration of mixed latches and flops showed promising results.
AB - Latches are extensively used in high-performance sequential circuit designs to achieve high frequencies because of their good performance and time borrowing feature. However, the amount of timing uncertainty due to crosstalk accumulated through latches could be larger than the benefit gained by time borrowing. In this paper, we show that the trade-off between a latch and a flop can be leveraged in a sequential circuit design with crosstalk, so that the clock period is minimized by selecting a configuration of mixed latches and flops. A circular time representation is proposed to make coupling detection easier and more efficient. Experiments on our heuristic algorithm for finding an optimal configuration of mixed latches and flops showed promising results.
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U2 - 10.1109/ICCAD.2005.1560089
DO - 10.1109/ICCAD.2005.1560089
M3 - Conference contribution
AN - SCOPUS:33751424102
SN - 078039254X
SN - 9780780392540
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 329
EP - 334
BT - Proceedings of theICCAD-2005
T2 - ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005
Y2 - 6 November 2005 through 10 November 2005
ER -