Tradeoff between latch and flop for min-period sequential circuit designs with crosstalk

Chuan Lin*, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Latches are extensively used in high-performance sequential circuit designs to achieve high frequencies because of their good performance and time-borrowing feature. However, the amount of timing uncertainty due to crosstalk accumulated through latches could be larger than the benefit gained by time borrowing. In this paper, we show that the tradeoff between a latch and a flop can be leveraged in a sequential circuit design with crosstalk, so that the clock period is minimized by selecting a configuration of mixed latches and flops. A circular time representation is proposed to make coupling detection easier and more efficient. Experiments on our heuristic algorithm for finding an optimal configuration of mixed latches and flops showed promising results.

Original languageEnglish (US)
Article number4237236
Pages (from-to)1222-1232
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume26
Issue number7
DOIs
StatePublished - Jul 2007

Keywords

  • Algorithms
  • Circuit optimization
  • Crosstalk
  • Design automation
  • Timing
  • Timing circuits
  • Very large scale integration

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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