This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of the design as well as practical uses such as in a small camera, or for use as an educational tool.
- Frame buffer
- Hardware description
ASJC Scopus subject areas
- Civil and Structural Engineering
- Biomedical Engineering
- Mechanical Engineering
- Industrial and Manufacturing Engineering