Triple frame buffer FPGA implementation

James Williams; Ilya Mikhelson

doi:10.1016/j.ohx.2019.e00064

Triple frame buffer FPGA implementation

James Williams^*, Ilya Mikhelson

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of the design as well as practical uses such as in a small camera, or for use as an educational tool.

Original language	English (US)
Article number	e00064
Journal	HardwareX
Volume	5
DOIs	https://doi.org/10.1016/j.ohx.2019.e00064
State	Published - Apr 2019

Keywords

Camera
Education
FPGA
Frame buffer
Hardware description
Verilog

ASJC Scopus subject areas

Civil and Structural Engineering
Biomedical Engineering
Instrumentation
Mechanical Engineering
Industrial and Manufacturing Engineering

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10.1016/j.ohx.2019.e00064

Cite this

@article{08ddf5cdf0784c8caddaee42d6d61099,

title = "Triple frame buffer FPGA implementation",

abstract = "This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of the design as well as practical uses such as in a small camera, or for use as an educational tool.",

keywords = "Camera, Education, FPGA, Frame buffer, Hardware description, Verilog",

author = "James Williams and Ilya Mikhelson",

note = "Publisher Copyright: {\textcopyright} 2019 The Authors",

year = "2019",

month = apr,

doi = "10.1016/j.ohx.2019.e00064",

language = "English (US)",

volume = "5",

journal = "HardwareX",

issn = "2468-0672",

publisher = "Elsevier Ltd",

}

TY - JOUR

T1 - Triple frame buffer FPGA implementation

AU - Williams, James

AU - Mikhelson, Ilya

PY - 2019/4

Y1 - 2019/4

N2 - This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of the design as well as practical uses such as in a small camera, or for use as an educational tool.

AB - This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of the design as well as practical uses such as in a small camera, or for use as an educational tool.

KW - Camera

KW - Education

KW - FPGA

KW - Frame buffer

KW - Hardware description

KW - Verilog

UR - http://www.scopus.com/inward/record.url?scp=85065165924&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85065165924&partnerID=8YFLogxK

U2 - 10.1016/j.ohx.2019.e00064

DO - 10.1016/j.ohx.2019.e00064

M3 - Article

AN - SCOPUS:85065165924

SN - 2468-0672

VL - 5

JO - HardwareX

JF - HardwareX

M1 - e00064

ER -

Triple frame buffer FPGA implementation

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

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