Ultra-low-power, high-density spintronic programmable logic (SPL)

Kang L. Wang; Hochul Lee; Farbod Ebrahimi; Pedram Khalili Amiri

doi:10.1109/ISCAS.2016.7527197

Ultra-low-power, high-density spintronic programmable logic (SPL)

Kang L. Wang, Hochul Lee, Farbod Ebrahimi, Pedram Khalili Amiri

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

A non-volatile spintronic programmable logic (SPL), based on a 3-teriminal magnetic tunnel junction (MTJ), is presented and simulated using a compact device model. The SPL structure is compatible with CMOS technology and can be fabricated in the back end of line (BEOL). The proposed SPL exploits the gate-voltage-modulated spin Hall effect (V-SHE) switching, which combines the voltage controlled magnetic anisotropy (VCMA) effect and SHE, as a parallel configuration method. The VCMA modulates the coercivity of the MTJ, reducing the critical current for the SHE to change the state of MTJs. This allows the SPL to achieve 100x faster configuration speed due to the parallel configuration, and 32% area reduction because of minimized transistors in the write circuit, compared to conventional spin transfer torque memory (STT-RAM) based programmable logic.

Original language	English (US)
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	169-172
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527197
State	Published - Jul 29 2016
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: May 22 2016 → May 25 2016

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July
ISSN (Print)	0271-4310

Other

Other	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Country/Territory	Canada
City	Montreal
Period	5/22/16 → 5/25/16

Keywords

Spin Electronics
gate-voltage-modulated SHE switching
magnetic tunnel junction (MTJ)
perpendicular magnetic anisotropy (PMA)
spin Hall effect (SHE)
voltage controlled magnetic anisotropy (VCMA)

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2016.7527197

Cite this

Wang, K. L., Lee, H., Ebrahimi, F., & Amiri, P. K. (2016). Ultra-low-power, high-density spintronic programmable logic (SPL). In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (pp. 169-172). Article 7527197 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7527197

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title = "Ultra-low-power, high-density spintronic programmable logic (SPL)",

abstract = "A non-volatile spintronic programmable logic (SPL), based on a 3-teriminal magnetic tunnel junction (MTJ), is presented and simulated using a compact device model. The SPL structure is compatible with CMOS technology and can be fabricated in the back end of line (BEOL). The proposed SPL exploits the gate-voltage-modulated spin Hall effect (V-SHE) switching, which combines the voltage controlled magnetic anisotropy (VCMA) effect and SHE, as a parallel configuration method. The VCMA modulates the coercivity of the MTJ, reducing the critical current for the SHE to change the state of MTJs. This allows the SPL to achieve 100x faster configuration speed due to the parallel configuration, and 32% area reduction because of minimized transistors in the write circuit, compared to conventional spin transfer torque memory (STT-RAM) based programmable logic.",

keywords = "Spin Electronics, gate-voltage-modulated SHE switching, magnetic tunnel junction (MTJ), perpendicular magnetic anisotropy (PMA), spin Hall effect (SHE), voltage controlled magnetic anisotropy (VCMA)",

author = "Wang, {Kang L.} and Hochul Lee and Farbod Ebrahimi and Amiri, {Pedram Khalili}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 ; Conference date: 22-05-2016 Through 25-05-2016",

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Wang, KL, Lee, H, Ebrahimi, F & Amiri, PK 2016, Ultra-low-power, high-density spintronic programmable logic (SPL). in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7527197, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, Institute of Electrical and Electronics Engineers Inc., pp. 169-172, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 5/22/16. https://doi.org/10.1109/ISCAS.2016.7527197

Ultra-low-power, high-density spintronic programmable logic (SPL). / Wang, Kang L.; Lee, Hochul; Ebrahimi, Farbod et al.
ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2016. p. 169-172 7527197 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Wang, Kang L.

AU - Lee, Hochul

AU - Ebrahimi, Farbod

AU - Amiri, Pedram Khalili

PY - 2016/7/29

Y1 - 2016/7/29

N2 - A non-volatile spintronic programmable logic (SPL), based on a 3-teriminal magnetic tunnel junction (MTJ), is presented and simulated using a compact device model. The SPL structure is compatible with CMOS technology and can be fabricated in the back end of line (BEOL). The proposed SPL exploits the gate-voltage-modulated spin Hall effect (V-SHE) switching, which combines the voltage controlled magnetic anisotropy (VCMA) effect and SHE, as a parallel configuration method. The VCMA modulates the coercivity of the MTJ, reducing the critical current for the SHE to change the state of MTJs. This allows the SPL to achieve 100x faster configuration speed due to the parallel configuration, and 32% area reduction because of minimized transistors in the write circuit, compared to conventional spin transfer torque memory (STT-RAM) based programmable logic.

AB - A non-volatile spintronic programmable logic (SPL), based on a 3-teriminal magnetic tunnel junction (MTJ), is presented and simulated using a compact device model. The SPL structure is compatible with CMOS technology and can be fabricated in the back end of line (BEOL). The proposed SPL exploits the gate-voltage-modulated spin Hall effect (V-SHE) switching, which combines the voltage controlled magnetic anisotropy (VCMA) effect and SHE, as a parallel configuration method. The VCMA modulates the coercivity of the MTJ, reducing the critical current for the SHE to change the state of MTJs. This allows the SPL to achieve 100x faster configuration speed due to the parallel configuration, and 32% area reduction because of minimized transistors in the write circuit, compared to conventional spin transfer torque memory (STT-RAM) based programmable logic.

KW - Spin Electronics

KW - gate-voltage-modulated SHE switching

KW - magnetic tunnel junction (MTJ)

KW - perpendicular magnetic anisotropy (PMA)

KW - spin Hall effect (SHE)

KW - voltage controlled magnetic anisotropy (VCMA)

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BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 22 May 2016 through 25 May 2016

ER -

Ultra-low-power, high-density spintronic programmable logic (SPL)

Abstract

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Keywords

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