TY - GEN
T1 - Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
AU - Gupta, Meeta S.
AU - Oatley, Jarod L.
AU - Joseph, Russell E
AU - Wei, Gu Yeon
AU - Brooks, David M.
PY - 2007
Y1 - 2007
N2 - Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. These variations, primarily due to fast changes in supply current, can be attributed to architectural gating events that reduce power dissipation. In order to study this problem, we propose a fine-grain, parameterizable model for power-delivery networks that allows system designers to study localized, on-chip supply fluctuations in high-performance microprocessors. Using this model, we analyze voltage variations in the context of next-generation chip-multiprocessor (CMP) architectures using both real applications and synthetic current traces. We find that the activity of distinct cores in CMPs present several new design challenges when considering power supply noise, and we describe potentially problematic activity sequences that are unique to CMP architectures.
AB - Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. These variations, primarily due to fast changes in supply current, can be attributed to architectural gating events that reduce power dissipation. In order to study this problem, we propose a fine-grain, parameterizable model for power-delivery networks that allows system designers to study localized, on-chip supply fluctuations in high-performance microprocessors. Using this model, we analyze voltage variations in the context of next-generation chip-multiprocessor (CMP) architectures using both real applications and synthetic current traces. We find that the activity of distinct cores in CMPs present several new design challenges when considering power supply noise, and we describe potentially problematic activity sequences that are unique to CMP architectures.
UR - http://www.scopus.com/inward/record.url?scp=34548348855&partnerID=8YFLogxK
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U2 - 10.1109/DATE.2007.364663
DO - 10.1109/DATE.2007.364663
M3 - Conference contribution
AN - SCOPUS:34548348855
SN - 3981080122
SN - 9783981080124
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 624
EP - 629
BT - Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
T2 - 2007 Design, Automation and Test in Europe Conference and Exhibition
Y2 - 16 April 2007 through 20 April 2007
ER -