Understanding voltage variations in chip multiprocessors using a distributed power-delivery network

Meeta S. Gupta*, Jarod L. Oatley, Russell E Joseph, Gu Yeon Wei, David M. Brooks

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

160 Scopus citations

Abstract

Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. These variations, primarily due to fast changes in supply current, can be attributed to architectural gating events that reduce power dissipation. In order to study this problem, we propose a fine-grain, parameterizable model for power-delivery networks that allows system designers to study localized, on-chip supply fluctuations in high-performance microprocessors. Using this model, we analyze voltage variations in the context of next-generation chip-multiprocessor (CMP) architectures using both real applications and synthetic current traces. We find that the activity of distinct cores in CMPs present several new design challenges when considering power supply noise, and we describe potentially problematic activity sequences that are unique to CMP architectures.

Original languageEnglish (US)
Title of host publicationProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
Pages624-629
Number of pages6
DOIs
StatePublished - 2007
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other2007 Design, Automation and Test in Europe Conference and Exhibition
Country/TerritoryFrance
CityNice Acropolis
Period4/16/074/20/07

ASJC Scopus subject areas

  • General Engineering

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