TY - GEN
T1 - VaLHALLA
T2 - 27th Great Lakes Symposium on VLSI, GLSVLSI 2017
AU - Gok, Ali Murat
AU - Hardavellas, Nikos
N1 - Funding Information:
This work was supported by NSF awards CCF-1218768 and CCF-1453853
PY - 2017/5/10
Y1 - 2017/5/10
N2 - Current low-energy adder designs fail to address subtraction or signed operations, are imprecise, or have large overheads. These overheads include overlapping sub-adders, relatively complex carry speculation mechanisms and bulky error correction circuits, all of which consume considerable amount of energy. In this paper, we address all these problems and introduce Variable Latency History Aware Local-carry Lazy Adder (VaLHALLA). VaLHALLA employs sliced non-overlapping sub-adders and speculates the carry-ins for each slice by exploiting the temporal operand correlation of each instruction location (i.e., it considers both operand history and instruction locale). VaLHALLA achieves accurate results at lower energy-delay-product than competing designs.
AB - Current low-energy adder designs fail to address subtraction or signed operations, are imprecise, or have large overheads. These overheads include overlapping sub-adders, relatively complex carry speculation mechanisms and bulky error correction circuits, all of which consume considerable amount of energy. In this paper, we address all these problems and introduce Variable Latency History Aware Local-carry Lazy Adder (VaLHALLA). VaLHALLA employs sliced non-overlapping sub-adders and speculates the carry-ins for each slice by exploiting the temporal operand correlation of each instruction location (i.e., it considers both operand history and instruction locale). VaLHALLA achieves accurate results at lower energy-delay-product than competing designs.
KW - Power efficiency
KW - Speculative adders
KW - Variable latency adders
UR - http://www.scopus.com/inward/record.url?scp=85021192552&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85021192552&partnerID=8YFLogxK
U2 - 10.1145/3060403.3060437
DO - 10.1145/3060403.3060437
M3 - Conference contribution
AN - SCOPUS:85021192552
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 17
EP - 22
BT - GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PB - Association for Computing Machinery
Y2 - 10 May 2017 through 12 May 2017
ER -