VaLHALLA: Variable latency history aware local-carry lazy adder

Ali Murat Gok; Nikos Hardavellas

doi:10.1145/3060403.3060437

VaLHALLA: Variable latency history aware local-carry lazy adder

Ali Murat Gok, Nikos Hardavellas

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Current low-energy adder designs fail to address subtraction or signed operations, are imprecise, or have large overheads. These overheads include overlapping sub-adders, relatively complex carry speculation mechanisms and bulky error correction circuits, all of which consume considerable amount of energy. In this paper, we address all these problems and introduce Variable Latency History Aware Local-carry Lazy Adder (VaLHALLA). VaLHALLA employs sliced non-overlapping sub-adders and speculates the carry-ins for each slice by exploiting the temporal operand correlation of each instruction location (i.e., it considers both operand history and instruction locale). VaLHALLA achieves accurate results at lower energy-delay-product than competing designs.

Original language	English (US)
Title of host publication	GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
Publisher	Association for Computing Machinery
Pages	17-22
Number of pages	6
ISBN (Electronic)	9781450349727
DOIs	https://doi.org/10.1145/3060403.3060437
State	Published - May 10 2017
Event	27th Great Lakes Symposium on VLSI, GLSVLSI 2017 - Banff, Canada Duration: May 10 2017 → May 12 2017

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume	Part F127756

Other

Other	27th Great Lakes Symposium on VLSI, GLSVLSI 2017
Country/Territory	Canada
City	Banff
Period	5/10/17 → 5/12/17

Funding

This work was supported by NSF awards CCF-1218768 and CCF-1453853

Keywords

Power efficiency
Speculative adders
Variable latency adders

ASJC Scopus subject areas

General Engineering

Access to Document

10.1145/3060403.3060437

Cite this

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title = "VaLHALLA: Variable latency history aware local-carry lazy adder",

abstract = "Current low-energy adder designs fail to address subtraction or signed operations, are imprecise, or have large overheads. These overheads include overlapping sub-adders, relatively complex carry speculation mechanisms and bulky error correction circuits, all of which consume considerable amount of energy. In this paper, we address all these problems and introduce Variable Latency History Aware Local-carry Lazy Adder (VaLHALLA). VaLHALLA employs sliced non-overlapping sub-adders and speculates the carry-ins for each slice by exploiting the temporal operand correlation of each instruction location (i.e., it considers both operand history and instruction locale). VaLHALLA achieves accurate results at lower energy-delay-product than competing designs.",

keywords = "Power efficiency, Speculative adders, Variable latency adders",

author = "Gok, {Ali Murat} and Nikos Hardavellas",

note = "Funding Information: This work was supported by NSF awards CCF-1218768 and CCF-1453853; 27th Great Lakes Symposium on VLSI, GLSVLSI 2017 ; Conference date: 10-05-2017 Through 12-05-2017",

year = "2017",

month = may,

day = "10",

doi = "10.1145/3060403.3060437",

language = "English (US)",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

publisher = "Association for Computing Machinery",

pages = "17--22",

booktitle = "GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017",

}

Gok, AM & Hardavellas, N 2017, VaLHALLA: Variable latency history aware local-carry lazy adder. in GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, vol. Part F127756, Association for Computing Machinery, pp. 17-22, 27th Great Lakes Symposium on VLSI, GLSVLSI 2017, Banff, Canada, 5/10/17. https://doi.org/10.1145/3060403.3060437

VaLHALLA: Variable latency history aware local-carry lazy adder. / Gok, Ali Murat; Hardavellas, Nikos.
GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017. Association for Computing Machinery, 2017. p. 17-22 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. Part F127756).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This work was supported by NSF awards CCF-1218768 and CCF-1453853

PY - 2017/5/10

Y1 - 2017/5/10

N2 - Current low-energy adder designs fail to address subtraction or signed operations, are imprecise, or have large overheads. These overheads include overlapping sub-adders, relatively complex carry speculation mechanisms and bulky error correction circuits, all of which consume considerable amount of energy. In this paper, we address all these problems and introduce Variable Latency History Aware Local-carry Lazy Adder (VaLHALLA). VaLHALLA employs sliced non-overlapping sub-adders and speculates the carry-ins for each slice by exploiting the temporal operand correlation of each instruction location (i.e., it considers both operand history and instruction locale). VaLHALLA achieves accurate results at lower energy-delay-product than competing designs.

AB - Current low-energy adder designs fail to address subtraction or signed operations, are imprecise, or have large overheads. These overheads include overlapping sub-adders, relatively complex carry speculation mechanisms and bulky error correction circuits, all of which consume considerable amount of energy. In this paper, we address all these problems and introduce Variable Latency History Aware Local-carry Lazy Adder (VaLHALLA). VaLHALLA employs sliced non-overlapping sub-adders and speculates the carry-ins for each slice by exploiting the temporal operand correlation of each instruction location (i.e., it considers both operand history and instruction locale). VaLHALLA achieves accurate results at lower energy-delay-product than competing designs.

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VaLHALLA: Variable latency history aware local-carry lazy adder

Abstract

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Funding

Keywords

ASJC Scopus subject areas

Access to Document

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