VaLHALLA: Variable latency history aware local-carry lazy adder

Ali Murat Gok, Nikos Hardavellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Current low-energy adder designs fail to address subtraction or signed operations, are imprecise, or have large overheads. These overheads include overlapping sub-adders, relatively complex carry speculation mechanisms and bulky error correction circuits, all of which consume considerable amount of energy. In this paper, we address all these problems and introduce Variable Latency History Aware Local-carry Lazy Adder (VaLHALLA). VaLHALLA employs sliced non-overlapping sub-adders and speculates the carry-ins for each slice by exploiting the temporal operand correlation of each instruction location (i.e., it considers both operand history and instruction locale). VaLHALLA achieves accurate results at lower energy-delay-product than competing designs.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PublisherAssociation for Computing Machinery
Pages17-22
Number of pages6
ISBN (Electronic)9781450349727
DOIs
StatePublished - May 10 2017
Event27th Great Lakes Symposium on VLSI, GLSVLSI 2017 - Banff, Canada
Duration: May 10 2017May 12 2017

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
VolumePart F127756

Other

Other27th Great Lakes Symposium on VLSI, GLSVLSI 2017
CountryCanada
CityBanff
Period5/10/175/12/17

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Keywords

  • Power efficiency
  • Speculative adders
  • Variable latency adders

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Gok, A. M., & Hardavellas, N. (2017). VaLHALLA: Variable latency history aware local-carry lazy adder. In GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017 (pp. 17-22). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. Part F127756). Association for Computing Machinery. https://doi.org/10.1145/3060403.3060437