Via-aware global routing for good VLSI manufacturability and high yield

Yang Yang*, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in which physical design tool is an essential and critical part. We try to consider the via minimization problem as early as possible in physical design. We propose a routing method focusing on minimizing vias while considering routability and wire-length constraint. That is, in the global routing phase, we minimize the number of bends, which is closely related to the number of vias. Previous work only dealt with very small nets, but our algorithm is general for the nets with any size. Experimental results show that our algorithm can greatly reduce the count of bends for various sizes of nets while meeting the constraints of congestion and wire-length.

Original languageEnglish (US)
Title of host publicationProceedings - 16th International Conference on Application-Specific Systems, Architectures, and Processors
Pages198-203
Number of pages6
DOIs
StatePublished - 2005
EventIEEE 16th International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2005 - Samos, Greece
Duration: Jul 23 2005Jul 25 2005

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN (Print)1063-6862

Other

OtherIEEE 16th International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2005
CountryGreece
CitySamos
Period7/23/057/25/05

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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    Yang, Y., Jing, T., Hong, X., Hu, Y., Zhu, Q., Hu, X., & Yan, G. (2005). Via-aware global routing for good VLSI manufacturability and high yield. In Proceedings - 16th International Conference on Application-Specific Systems, Architectures, and Processors (pp. 198-203). (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors). https://doi.org/10.1109/ASAP.2005.67