TY - GEN
T1 - Via-aware global routing for good VLSI manufacturability and high yield
AU - Yang, Yang
AU - Jing, Tong
AU - Hong, Xianlong
AU - Hu, Yu
AU - Zhu, Qi
AU - Hu, Xiaodong
AU - Yan, Guiying
N1 - Copyright:
Copyright 2011 Elsevier B.V., All rights reserved.
PY - 2005
Y1 - 2005
N2 - CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in which physical design tool is an essential and critical part. We try to consider the via minimization problem as early as possible in physical design. We propose a routing method focusing on minimizing vias while considering routability and wire-length constraint. That is, in the global routing phase, we minimize the number of bends, which is closely related to the number of vias. Previous work only dealt with very small nets, but our algorithm is general for the nets with any size. Experimental results show that our algorithm can greatly reduce the count of bends for various sizes of nets while meeting the constraints of congestion and wire-length.
AB - CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in which physical design tool is an essential and critical part. We try to consider the via minimization problem as early as possible in physical design. We propose a routing method focusing on minimizing vias while considering routability and wire-length constraint. That is, in the global routing phase, we minimize the number of bends, which is closely related to the number of vias. Previous work only dealt with very small nets, but our algorithm is general for the nets with any size. Experimental results show that our algorithm can greatly reduce the count of bends for various sizes of nets while meeting the constraints of congestion and wire-length.
UR - http://www.scopus.com/inward/record.url?scp=24944519466&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=24944519466&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2005.67
DO - 10.1109/ASAP.2005.67
M3 - Conference contribution
AN - SCOPUS:24944519466
SN - 0769524079
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 198
EP - 203
BT - Proceedings - 16th International Conference on Application-Specific Systems, Architectures, and Processors
T2 - IEEE 16th International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2005
Y2 - 23 July 2005 through 25 July 2005
ER -