Via-aware global routing for good VLSI manufacturability and high yield

Keyphrases

• Manufacturability 100%
• Physical Design 100%
• Global Routing 100%
• Wirelength 100%
• On-a-chip 50%
• Minimization Problem 50%
• Single chip 50%
• Congestion 50%
• Design Tools 50%
• Complicated System 50%
• Integrated Circuit Design 50%
• CAD Tools 50%
• Routability 50%
• Routing Method 50%
• Length Constraint 50%
• Number of Bends 50%
• Via Minimization 50%

Engineering

• Experimental Result 100%
• Manufacturability 100%
• Integrated Circuit Design 100%
• Minimization Problem 100%
• Single Chip 100%
• Constraint Length 100%
• Design Tool 100%
• Computer Aided Design 100%

Computer Science

• Global Routing 100%
• Physical Design 100%
• Integrated Circuit Design 50%
• System on a Chip 50%
• single-chip 50%
• Experimental Result 50%
• Minimization Problem 50%
• Computer Aided Design 50%
• Design Tool 50%