Abstract
Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they characterize the implications of resilient architecture design for voltage variation in future systems.
Original language | English (US) |
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Article number | 5661758 |
Pages (from-to) | 20-28 |
Number of pages | 9 |
Journal | IEEE Micro |
Volume | 31 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2011 |
Keywords
- Software thread scheduling
- dI/dt
- inductive noise
- processor design
- voltage margins
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering