Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling

Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu Yeon Wei, David Brooks

Research output: Chapter in Book/Report/Conference proceedingConference contribution

58 Scopus citations

Abstract

Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel ® Core™2 Duo processor. By sensing on-die voltage as the processor runs singlethreaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4%, far from the processor's 14% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15% to 20% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show that a voltagenoise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.

Original languageEnglish (US)
Title of host publicationProceedings - 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010
Pages77-88
Number of pages12
DOIs
StatePublished - 2010
Event43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010 - Atlanta, GA, United States
Duration: Dec 4 2010Dec 8 2010

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

Other43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010
CountryUnited States
CityAtlanta, GA
Period12/4/1012/8/10

Keywords

  • DI/dt
  • Error resiliency
  • Hardware reliability
  • Hw/sw co-design
  • Inductive noise
  • Thread scheduling
  • Voltage droop

ASJC Scopus subject areas

  • Hardware and Architecture

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