Wall: A writeback-Aware LLC management for pcm-based main memory systems

Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this paper, we propose WALL, a novel writeback-Aware LLC management scheme to reduce the number of LLC writebacks and consequently improve performance, energy efficiency, and lifetime of a PCM-based main memory system. First, we investigate the writeback behavior of LLC sets and show that writebacks are not uniformly distributed among sets; some sets observe much higher writeback rates than others. We then propose a writeback-Aware set-balancing mechanism, which employs the underutilized LLC sets with few writebacks as an auxiliary storage for storing the evicted dirty lines of sets with frequent writebacks. We also propose a simple and effective writeback-Aware replacement policy to avoid the eviction of the writeback blocks that are highly reused after being evicted from the cache. Our experimental results show that WALL achieves an average of 26.6% reduction in the total number of LLC writebacks, compared to the baseline scheme, which uses the LRU replacement policy. As a result, WALL can reduce the memory energy consumption by 19.2% and enhance PCM lifetime by 1.25x, on average, on an 8-core system with a 4GB PCM main memory, running memory intensive applications.

Original languageEnglish (US)
Title of host publicationProceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages449-454
Number of pages6
ISBN (Electronic)9783981926316
DOIs
StatePublished - Apr 19 2018
Event2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany
Duration: Mar 19 2018Mar 23 2018

Publication series

NameProceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
Volume2018-January

Other

Other2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
CountryGermany
CityDresden
Period3/19/183/23/18

Keywords

  • Energy consumption
  • Last level cache
  • Performance
  • Phace change memory
  • Write endurance

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Software
  • Information Systems and Management

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  • Cite this

    Pourshirazi, B., Beigi, M. V., Zhu, Z., & Memik, G. (2018). Wall: A writeback-Aware LLC management for pcm-based main memory systems. In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 (pp. 449-454). (Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE.2018.8342051