Abstract
In system-on-chips (SOCs), a nonnegligible part of operation time is spent on global wires with long delays. Retiming-that is moving flip-flops in a circuit without changing its functionality-can be explored to pipeline long interconnect wires in SOC designs. The problem of retiming over a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be inserted on some wire segments is called the wire retiming problem. In this paper, we formulate the constraints of the wire retiming problem as a flxpoint computation and use an iterative algorithm to solve it. Experimental results show that this approach is multiple orders more efficient than the previous one.
Original language | English (US) |
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Pages (from-to) | 1340-1348 |
Number of pages | 9 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 13 |
Issue number | 12 |
DOIs | |
State | Published - Dec 2005 |
Keywords
- Algorithms
- Circuit modeling
- Circuit optimization
- Fixpoint
- Interconnects
- Retiming
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering