Abstract
With the increase in the number of data-intensive applications on today's workloads, DRAM-based main memories are struggling to satisfy the growing data demand capacity. Phase Change Memory (PCM) is a type of non-volatile memory technology that has been explored as a promising alternative for DRAM-based main memories due to its better scalability and lower leakage energy. Despite its many advantages, PCM also has shortcomings such as long write latency, high write energy consumption, and limited write endurance, which are all related to the write operations. In this article, we propose a novel writeback-aware Last Level Cache (LLC) management scheme named WALL to reduce the number of LLC writebacks and consequently improve performance, energy efficiency, and lifetime of a PCM-based main memory system. First, we investigate the writeback behavior of LLC sets and show that writebacks are not uniformly distributed among sets; some sets observe much higher writeback rates than others. We then propose a writeback-aware set-balancing mechanism, which employs the underutilized LLC sets with few writebacks as an auxiliary storage for the evicted dirty lines from sets with frequent writebacks. We also propose a simple and effective writeback-aware replacement policy to avoid the eviction of the dirty blocks that are highly reused after being evicted from the cache. Our experimental results show that WALL achieves an average of 30.9% reduction in the total number of LLC writebacks, compared to the baseline scheme, which uses the LRU replacement policy. As a result, WALL can reduce the memory energy consumption by 23.1% and enhance PCM lifetime by 1.29×, on average, on an 8-core system with a 4GB PCM main memory, running memory-intensive applications.
| Original language | English (US) |
|---|---|
| Article number | a18 |
| Journal | ACM Transactions on Design Automation of Electronic Systems |
| Volume | 24 |
| Issue number | 2 |
| DOIs | |
| State | Published - Jan 2019 |
Funding
This work is an extension of our previous work, which is published on Proceedings of the Design, Automation, and Test in Europe 2018 (DATE’18) with the title “WALL: A Writeback-Aware LLC Management for PCM-based Main Memory Systems.” This work is supported in part by the National Science Foundation under Grant No. CCF-1513899. Authors’ addresses: B. Pourshirazi and Z. Zhu, Electrical and Computer Engineering Department, University of Illinois at Chicago, Chicago, IL 60607, USA; emails: {bpours2, zzhu}@uic.edu; M. Valad Beigi, Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL 60208, USA; email: [email protected]; G. Memik, Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL 60208, USA; email: [email protected]. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. © 2019 Association for Computing Machinery. 1084-4309/2019/01-ART18 $15.00 https://doi.org/10.1145/3292009
Keywords
- Energy consumption
- Last level cache
- Performance
- Phase change memory
- Write endurance
ASJC Scopus subject areas
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
