Yield driven gate sizing for coupling-noise reduction under uncertainty

Debjit Sinha; Hai Zhou

doi:10.1145/1120725.1120803

Yield driven gate sizing for coupling-noise reduction under uncertainty

Debjit Sinha^*, Hai Zhou

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noise reduction which do not consider uncertainty in the manufacturing process can make a circuit susceptible to failure. Using probabilistic models, the coupling-noise reduction problem is solved as a fixpoint computation problem on a lattice. A novel gate-sizing algorithm with low area overhead is proposed for coupling-noise reduction under uncertainty. Experimental results are reported for the ISCAS benchmarks and larger circuits with comparisons to traditional approaches.

Original language	English (US)
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	192-197
Number of pages	6
ISBN (Print)	0780387368, 9780780387362
DOIs	https://doi.org/10.1145/1120725.1120803
State	Published - Jan 1 2005
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: Jan 18 2005 → Jan 21 2005

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	1

Other

Other	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country	China
City	Shanghai
Period	1/18/05 → 1/21/05

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1145/1120725.1120803

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Sinha, D., & Zhou, H. (2005). Yield driven gate sizing for coupling-noise reduction under uncertainty. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 192-197). [1466156] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1120725.1120803

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title = "Yield driven gate sizing for coupling-noise reduction under uncertainty",

abstract = "This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noise reduction which do not consider uncertainty in the manufacturing process can make a circuit susceptible to failure. Using probabilistic models, the coupling-noise reduction problem is solved as a fixpoint computation problem on a lattice. A novel gate-sizing algorithm with low area overhead is proposed for coupling-noise reduction under uncertainty. Experimental results are reported for the ISCAS benchmarks and larger circuits with comparisons to traditional approaches.",

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booktitle = "Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005",

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Sinha, D & Zhou, H 2005, Yield driven gate sizing for coupling-noise reduction under uncertainty. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466156, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 192-197, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 1/18/05. https://doi.org/10.1145/1120725.1120803

Yield driven gate sizing for coupling-noise reduction under uncertainty. / Sinha, Debjit; Zhou, Hai.

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc., 2005. p. 192-197 1466156 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noise reduction which do not consider uncertainty in the manufacturing process can make a circuit susceptible to failure. Using probabilistic models, the coupling-noise reduction problem is solved as a fixpoint computation problem on a lattice. A novel gate-sizing algorithm with low area overhead is proposed for coupling-noise reduction under uncertainty. Experimental results are reported for the ISCAS benchmarks and larger circuits with comparisons to traditional approaches.

AB - This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noise reduction which do not consider uncertainty in the manufacturing process can make a circuit susceptible to failure. Using probabilistic models, the coupling-noise reduction problem is solved as a fixpoint computation problem on a lattice. A novel gate-sizing algorithm with low area overhead is proposed for coupling-noise reduction under uncertainty. Experimental results are reported for the ISCAS benchmarks and larger circuits with comparisons to traditional approaches.

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BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

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Sinha D, Zhou H. Yield driven gate sizing for coupling-noise reduction under uncertainty. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc. 2005. p. 192-197. 1466156. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1145/1120725.1120803

Yield driven gate sizing for coupling-noise reduction under uncertainty

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